Effective Routing Technique Based on Decision Logic for Open Faults in Fpgas Interconnects

In this paper, different routing techniques using decision logic with identity circuit to identify the faulty element in FPGA interconnects are presented. The fault model we use here is stuck-open and resistive-open for interconnects. This technique is implemented in FPGA chips and verified using fault emulation. Failure analysis and the yield enhancement process are done by using high resolution routing. Open faults are the most common type of defect in deep sub-micron technology. An open fault is discontinuity in the connection between two circuit nodes that should be completely connected. A minor discontinuity results in resistive connection. A fault can be avoided by using another configuration which implements the same functionality but avoids the faulty elements. So a fast and high resolution routing technique is exploited to allow the use of defective chips and can also be used as fault tolerant schemes.